Recently, it has been raised of a need to make, in using memories, even undesirable occurrences of malfunctions due to external noises, power-down, and management by a short-handed user, be impossible to destroy data stored in the memories. In order to provide the safekeeping to the stored data, lockable cells have been proposed in the memories, in which a lockable cell is arranged to correspond to a unit of page (basically referred to a construction of memory cells coupled to a word line) and stores an information of erasure lock or unlock. A foregone technique about the lockable cell, as an example, is disclosed in Korean Application No.94-20426.
FIG. 1 shows a general construction of a memory cell array having lockable cells, in which block selection circuit 1, pass transistor array 2, memory cell array 3, lockable cell array 4 and lockable pass transistor array 5 are arranged. Block selection circuit 1 applies page selection control signal PGATE to pass transistor array 2. Memory cell array 3 is constituted of a plurality of strings in which a plurality of memory cell transistors M1n through M8n are coupled in serial between string selection transistor S1n and ground selection transistor G1n. Lockable cell array 4 is a string (or a lockable string) formed of a plurality of lockable cell transistors LM1n through LM8n serially coupled between lockable string selection transistor LS1n and lockable ground selection transistor LG1n. Gates of string selection transistors S1n and LS1n are coupled to string selection line SSL in common, and gates of ground selection transistors G1n and LG1n to ground selection line GSL in common. Pass transistor array 2 connects page selection signals S1 through S8 to word lines WL1 through WL8 of memory cell array 3 in response to page selection control signal PGATE. Lockable pass transistor array 5 connects lockable page selection signals LS1 through LS8 to lockable word lines LWL1 through LWL8 in response to PGATE. FIG. 2 shows a section along the word line in FIG. 1, which depicts that a terminal of erasure voltage Vera is connected to the bulk region including pocket P-well 8, N-well 7 and P-substrate 6. FIG. 3 illustrating an equivalent schematic about coupling capacitances involved in the word line by page in the array, where Cp denotes coupling capacitance of the word line at the side of the pass transistor array and Ca is coupling capacitance of the word line at the side of the memory cell array, and Clp and Cla is for the lockable cell array and lockable pass transistor array, will be referred to the following description about an operation of FIG. 1.
In FIG. 4, an erasure unlock operation begins when flag signal SUNLOCK for the unlock mode goes to high level. Responding to SUNLOCK of high level, page selection signals S1.about.S8 all go to high levels and a lockable page selection signal (one of LS1.about.LS8) corresponding to a selected cell retains low level while the other lockable page selection signals are pulled up to high levels. String and ground selection signals, SSL and GSL, go to high levels, and page selection control signal PGATE generated from block selection circuit 1 rises up to high level to make transistors SP1, MP1.about.MP8 and GP1 in pass transistor array 2 be turned on thereby. Then, the voltage of Vcc-Vth (Vcc is power source voltage and Vth is threshold voltage of the pass transistor) is applied to WL1.about.WL8. A lockable word line corresponding to a selected lockable cell transistor is held on 0 V while other lockable word lines are charged to the Vcc-Vth. In the mean time, erasure voltage Vera over about 20 V is applied to N-well 7 and pocket P-well 8 to charge up therein, as shown in FIG. 2, so that voltage levels of the word lines, Vboost1 for WL1.about.WL8 and Vboost2 for LWL1.about.LWL8, increase by capacitive coupling between the bulk region and themselves and arrive at the boosting levels as shown in FIG. 4. Exactly, the Vboost1 is the voltage on the word line in memory cell array 3 and pass transistor array 2, and Vboost2 is the voltage of the lockable word line correspond to the unselected lockable cell and pass transistors, during Vera is being applied thereto. Pass transistors, SP1, MP1.about.MP8 and GP1, and unselected lockable cell transistors are put into shut-off states. Lockable word lines corresponding to selected lockable cell transistors are held on 0 V. At this point, the Vboost1 and Vboost2 may meet the equations as follows; EQU Vboost1=Ca/(Ca+Cp).times.(Vera+Vcc-Vth), EQU Vboost2=Cla/(Cla+Clp).times.(Vera+Vcc-Vth).
Since the boosted voltages, Vboost1 and Vboost2, respectively on the word lines and unselected lockable word lines cause the corresponding cell transistors, i.e., memory cell transistors and unselected lockable cell transistors, to be situated in the condition to be not erased during the bulk erasure operation, all the cell transistors but the selected lockable cell transistor maintains their data while the selected lockable cell is erased to be changed to an unlock state from a lock state.
However, there would be a failure in the erasure blocking operation against the unselected lockable cell transistors. Referring to the equations for Vboost1 and Vboost2, Vboost2 would be less charged enough to prevent the unselected lockable cell transistors from being erased because Cla is lower than Clp, whereas Ca much larger than Cp in memory cell array can secure the erasure protecting effect against the memory cell transistors.